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| PDU13F 3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU13F) FEATURES * * * * * * * * Digitally programmable in 8 delay steps Monotonic delay-versus-address variation Two separate outputs: inverting & non-inverting Precise and stable delays Input & outputs fully TTL interfaced & buffered 10 T2L fan-out capability Fits standard 14-pin DIP socket Auto-insertable IN N/C N/C OUT OUT/ EN/ GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 data 3 delay devices, inc. PACKAGES VCC N/C N/C N/C A0 A1 A2 IN N/C N/C N/C OUT OUT/ EN/ GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC N/C N/C N/C A0 A1 A2 N/C PDU13F-xx PDU13F-xxA2 PDU13F-xxB2 PDU13F-xxM DIP Gull-Wing J-Lead Military DIP PDU13F-xxMC3 Military Gull-Wing FUNCTIONAL DESCRIPTION The PDU13F-series device is a 3-bit digitally programmable delay line. The delay, TDA, from the input pin (IN) to the output pins (OUT, OUT/) depends on the address code (A2-A0) according to the following formula: TDA = TD0 + TINC * A PIN DESCRIPTIONS IN OUT OUT/ A2 A1 A0 EN/ VCC GND Delay Line Input Non-inverted Output Inverted Output Address Bit 2 Address Bit 1 Address Bit 0 Output Enable +5 Volts Ground where A is the address code, TINC is the incremental delay of the device, and TD0 is the inherent delay of the device. The incremental delay is specified by the dash number of the device and can range from 0.5ns through 50ns, inclusively. The enable pin (EN/) is held LOW during normal operation. When this signal is brought HIGH, OUT and OUT/ are forced into LOW and HIGH states, respectively. The address is not latched and must remain asserted during normal operation. SERIES SPECIFICATIONS * * * * * * * * Total programmed delay tolerance: 5% or 1ns, whichever is greater Inherent delay (TD0): 6ns typical (OUT) 5.5ns typical (OUT/) Setup time and propagation delay: Address to input setup (TAIS): 6ns Disable to output delay (TDISO): 6ns typ. (OUT) Operating temperature: 0 to 70 C Temperature coefficient: 100PPM/C (excludes TD0) Supply voltage VCC: 5VDC 5% Supply current: ICCH = 45ma ICCL = 20ma Minimum pulse width: 20% of total delay DASH NUMBER SPECIFICATIONS Part Number PDU13F-.5 PDU13F-1 PDU13F-2 PDU13F-3 PDU13F-5 PDU13F-10 PDU13F-15 PDU13F-20 PDU13F-40 PDU13F-50 Incremental Delay Per Step (ns) .5 .3 1 .4 2 .4 3 .5 5 .6 10 1.0 15 1.3 20 1.5 40 2.0 50 2.5 Total Delay Change (ns) 3.5 1.0 7 1.0 14 1.0 21 1.1 35 1.8 70 3.5 105 5.3 140 7.0 280 14.0 350 17.5 NOTE: Any dash number between .5 and 50 not shown is also available. 2004 Data Delay Devices Doc #97001 3/25/04 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 1 PDU13F APPLICATION NOTES ADDRESS UPDATE The PDU13F is a memory device. As such, special precautions must be taken when changing the delay address in order to prevent spurious output signals. The timing restrictions are shown in Figure 1. After the last signal edge to be delayed has appeared on the OUT pin, a minimum time, TOAX, is required before the address lines can change. This time is given by the following relation: TOAX = max { (Ai - A i-1) * TINC , 0 } where A i-1 and Ai are the old and new address codes, respectively. Violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the OUT pin. The possibility of spurious signals persists until the required TOAX has elapsed. A similar situation occurs when using the EN/ signal to disable the output while IN is active. In this case, the unit must be held in the disabled state until the device is able to "clear" itself. This is achieved by holding the EN/ signal high and the IN signal low for a time given by: TDISH = Ai * TINC Violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the OUT pin. The possibility of spurious signals persists until the required TDISH has elapsed. INPUT RESTRICTIONS There are three types of restrictions on input pulse width and period listed in the AC Characteristics table. The recommended conditions are those for which the delay tolerance specifications and monotonicity are guaranteed. The suggested conditions are those for which signals will propagate through the unit without significant distortion. The absolute conditions are those for which the unit will produce some type of output for a given input. When operating the unit between the recommended and absolute conditions, the delays may deviate from their values at low frequency. However, these deviations will remain constant from pulse to pulse if the input pulse width and period remain fixed. In other words, the delay of the unit exhibits frequency and pulse width dependence when operated beyond the recommended conditions. Please consult the technical staff at Data Delay Devices if your application has specific high-frequency requirements. Please note that the increment tolerances listed represent a design goal. Although most delay increments will fall within tolerance, they are not guaranteed throughout the address range of the unit. Monotonicity is, however, guaranteed over all addresses. A2-A0 TAENS EN/ TENIS IN TDA OUT A i-1 TOAX PW IN PW OUT TSKEW TDISO TAIS Ai TDISH OUT/ Figure 1: Timing Diagram Doc #97001 3/25/04 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 2 PDU13F DEVICE SPECIFICATIONS TABLE 1: AC CHARACTERISTICS PARAMETER Total Programmable Delay Inherent Delay Output Skew Disable to Output Low Delay Address to Enable Setup Time Address to Input Setup Time Enable to Input Setup Time Output to Address Change Disable Hold Time Absolute Input Period Suggested Recommended Absolute Input Pulse Width Suggested Recommended SYMBOL TDT TD0 TSKEW TDISO TAENS TAIS TENIS TOAX TDISH PERIN PERIN PERIN PWIN PWIN PWIN MIN TYP 7 6.0 1.5 6.0 UNITS TINC ns ns ns ns ns ns 2.0 6.0 6.0 See Text See Text 20 50 200 10 25 100 % of TDT % of TDT % of TDT % of TDT % of TDT % of TDT TABLE 2: ABSOLUTE MAXIMUM RATINGS PARAMETER DC Supply Voltage Input Pin Voltage Storage Temperature Lead Temperature SYMBOL VCC VIN TSTRG TLEAD MIN -0.3 -0.3 -55 MAX 7.0 VDD+0.3 150 300 UNITS V V C C NOTES 10 sec TABLE 3: DC ELECTRICAL CHARACTERISTICS (0C to 70C, 4.75V to 5.25V) PARAMETER High Level Output Voltage Low Level Output Voltage High Level Output Current Low Level Output Current High Level Input Voltage Low Level Input Voltage Input Clamp Voltage Input Current at Maximum Input Voltage High Level Input Current Low Level Input Current Short-circuit Output Current Output High Fan-out Output Low Fan-out SYMBOL VOH VOL IOH IOL VIH VIL VIK IIHH IIH IIL IOS MIN 2.5 TYP 3.4 0.35 MAX 0.5 -1.0 20.0 2.0 0.8 -1.2 0.1 20 -0.6 -150 25 12.5 UNITS V V mA mA V V V mA A mA mA Unit Load NOTES VCC = MIN, IOH = MAX VIH = MIN, VIL = MAX VCC = MIN, IOL = MAX VIH = MIN, VIL = MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX -60 Doc #97001 3/25/04 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 3 PDU13F PACKAGE DIMENSIONS .020 TYP. 14 13 12 11 10 9 8 .040 TYP. 9 8 .010 TYP. 14 13 12 11 10 Lead Material: Nickel-Iron alloy 42 TIN PLATE 1 2 3 4 5 6 7 1 2 3 4 5 6 7 .270 TYP. .430 TYP. .090 .280 MAX. .290 MAX. .820 MAX. .100 .600 .790 MAX. .300 MAX. .050 TYP. Commercial Gull-Wing (PDU13F-xxA2) .020 TYP. 14 13 12 11 10 9 8 .040 TYP. .270 TYP. .050 TYP. .320 TYP. .015 TYP. .018 TYP. .070 MAX. .600.010 6 Equal spaces each .100.010 Non-Accumulative .010.002 1 2 3 4 5 6 7 .350 MAX. .110 .100 .600 .790 MAX. .350 MAX. .110 TYP. Commercial DIP (PDU13F-xx) Commercial J-Lead (PDU13F-xxB2) 14 13 12 11 10 9 8 .410 TYP. 12 3 4 5 6 7 .020 TYP. 16 15 14 13 12 11 10 9 .040 TYP. .010.002 .820 MAX. .020 .320 TYP. MAX. 1 2 3 4 5 6 7 8 .710 .590 .005 MAX. .882 .005 .007 .005 .130 .030 .018 TYP. .600 TYP. .100 TYP. .020 TYP. .300 TYP. .090 .700 .880.020 .100 .280 MAX. .050 .010 Military DIP (PDU13F-xxM) Military Gull-Wing (PDU13F-xxMC3) Doc #97001 3/25/04 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 4 PDU13F DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: Ambient Temperature: 25oC 3oC Supply Voltage (Vcc): 5.0V 0.1V Input Pulse: High = 3.0V 0.1V Low = 0.0V 0.1V Source Impedance: 50 Max. Rise/Fall Time: 3.0 ns Max. (measured between 0.6V and 2.4V ) Pulse Width: PWIN = 1.5 x Total Delay Period: PERIN = 4.5 x Total Delay OUTPUT: Load: Cload: Threshold: 1 FAST-TTL Gate 5pf 10% 1.5V (Rising & Falling) NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. COMPUTER SYSTEM PRINTER REF PULSE GENERATOR OUT TRIG IN DEVICE UNDER TEST (DUT) OUT IN TRIG TIME INTERVAL COUNTER Test Setup PERIN PW IN TRISE INPUT SIGNAL 2.4V 1.5V 0.6V TFALL VIH 2.4V 1.5V 0.6V VIL TDAF TDAR OUTPUT SIGNAL 1.5V VOH 1.5V VOL Timing Diagram For Testing Doc #97001 3/25/04 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 5 |
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